1. Field of the Invention
The present disclosure relates to low thermal budget schemes in semiconductor device fabrication, and, more particularly, to optimized low thermal budget schemes for improved performances of advanced semiconductor device structures.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently, and in the foreseeable future, the majority of integrated circuits are based on silicon devices, due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices.
One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. Another aspect of down-scaling transistors is the improved frequency response which is proportional to 1/L, L being the gate length. Furthermore, decreasing the channel length and the gate oxide thickness increases the current drive of a transistor.
In transistor elements, source and drain regions are provided by conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region. Upon applying a sufficiently high voltage signal to a gate electrode which is disposed on the active region, a conducting region in the crystalline active region between the source and drain regions is induced. Although the gate length has been reduced in efforts to obtain smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance at reduced gate lengths.
Many of the front-end-of-line (FEOL) fabrication processes involve implantation sequences in order to implement a specific dopant concentration profile in specific regions of a semiconductor substrate. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and, therefore, one or more anneal cycles are typically required for curing the crystal damages, while the dopants are also activated. For example, the electrical activation of implanted boron shows a relative maximum at temperatures of 500° C., where the dopants are incorporated and damages are healed. Increasing the temperature leads to increased accumulation of dopants at defects, while, upon further increasing the temperature, appropriate incorporation of dopants takes place.
In addition to dopant activation and curing of crystal damages, however, dopant diffusion occurs during annealing processes. Herein, dopant diffusion increases with increasing temperature, leading to a “blurring” of dopant profiles at high temperatures. For defining critical transistor properties, such as the overlap between the extension regions and the gate electrode, dopant diffusion may be advantageous. In other areas of the drain and source regions, dopant diffusion may be undesired, such as in deeper lying portions where the diffusion may reduce the dopant concentration at PN junction areas, thereby reducing the conductivity at the vicinity of these areas.
Thus, on the one hand, a high anneal temperature may be desirable in view of a high degree of dopant activation, re-crystallization of implantation-induced lattice damage and a desired diffusion at shallow areas of the extension regions, while, on the other hand, the duration of the anneal process should be short in order to restrict the degree of dopant diffusion in the deeper drain and source regions, which may reduce the dopant gradient at the respective PN junctions and also reduce the overall conductivity due to reducing the averaged dopant concentration.
Furthermore, very high temperatures during the anneal process may have a negative effect on gate insulation layers and reduce the reliability thereof. That is, high anneal temperatures may degrade the gate insulation layer and affect the dielectric characteristics thereof, resulting in increased leakage currents, reduced breakdown voltage and the like. Therefore, particularly in the case of highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, as the overall series resistance of the conductive path between the drain and source contacts may represent dominant parts for determining a transistor's performance.
Traditional rapid thermal anneal (RTA) processes are conventionally performed by heating the entire carrier material to a desired temperature. Alternatively, radiation-based anneal techniques have also been applied, which cause non-equilibrium conditions wherein a high amount of power is supplied within extremely short time intervals and thereby the required extremely high temperatures are provided. In advanced manufacturing regimes, traditional RTA processes are frequently supplemented (in the form of pre-anneal processes) or replaced by advanced radiation-based anneal processes in order to obtain a high degree of dopant activation and re-crystallization active regions. However, adjusting the effective channel length on the basis of a well-controlled diffusion of the dopants becomes more and more difficult in highly-integrated circuits having strongly scaled semiconductor devices, as pointed out above.
As the above-described state in the art does not comply with requirements on advanced semiconductor devices, there is a need for providing optimized process flows for FEOL processes which allow for the implementation of well-defined dopant profiles within sophisticated semiconductor devices.
It is desirable to provide methods of forming a semiconductor device that provide semiconductor devices or intermediate semiconductor device structures that show improved performance, particularly when high-k materials are employed, without introducing complex additional sequences into existing process flows.